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PhysicsMediumClass 12

Transistor — NPN/PNP, CE configuration

Semiconductor

11

JEE Qs

8%

Hard

75

min

Focus on consistently applying KVL to input and output loops along with current relations (I_E = I_B + I_C, I_C = beta * I_B) to solve numerical problems for CE configuration.

🧮 Key Formulas

I_E = I_B + I_C
beta_dc = I_C / I_B
alpha_dc = I_C / I_E
beta = alpha / (1 - alpha)
alpha = beta / (1 + beta)
Input Loop KVL (CE configuration, common setup): V_BB - I_B * R_B - V_BE = 0
Output Loop KVL (CE configuration, common setup): V_CC - I_C * R_C - V_CE = 0
Voltage Gain (A_v) = - beta_ac * (R_C / R_in_base)
Current Gain (A_i) = beta_ac
Power Gain (A_p) = A_v * A_i

✅ Key Points for JEE

  • 1Correctly identify NPN/PNP transistor symbols and direction of conventional current flow for emitter, base, and collector.
  • 2Understand that for a transistor to operate in the active region (as an amplifier), the emitter-base junction must be forward biased and the collector-base junction must be reverse biased.
  • 3Master the application of Kirchhoff's Voltage Law (KVL) to the input (base-emitter) and output (collector-emitter) loops to determine DC operating point (Q-point).
  • 4Memorize the fundamental current relations: I_E = I_B + I_C and I_C = beta * I_B. Be aware of the difference between DC current gain (beta_dc) and AC current gain (beta_ac).
  • 5Recognize the transistor's three regions of operation (active, saturation, cut-off) and their implications for biasing and output characteristics.

⚠️ Common Mistakes

  • Incorrectly identifying current directions for NPN vs. PNP transistors, leading to errors in KVL equations.
  • Forgetting to account for V_BE (typically ~0.7V for silicon) in the input loop KVL, or confusing V_CE with V_CB.
  • Confusing alpha (common base current gain) and beta (common emitter current gain) or their AC/DC versions, and using the wrong formula for their inter-relationship.
  • Applying KVL incorrectly, especially when multiple voltage sources or resistors are present in the base or collector circuits.

📝 Practice Questions

See all

Q27.Consider the following statements: A. The junction area of solar cell is made very narrow compared to a photo diode. B. Solar cells are not connected with any external bias. C. LED is made of lightly doped p-n junction. D. Increase of forward current results in continuous increase of LED light intensity. E. LEDs have to be connected in forward bias for emission of light. Choose the correct answer from the options given below: (1) B, E Only (2) B, D, E Only (3) A, C Only (4) A, C, E Only

2025·MCQMedium

Q43.Which of the following circuits has the same outpur as that of the given circuit? (1) (2) (3) (4)

2025·MCQMedium

Q33.Which of the following circuits represents a forward biased diode? Choose the correct answer from the options given below : (1) (A) and (D) only (2) (B), (D) and (E) only (3) (C) and (E) only (4) (B), (C) and (E) only

2025·ConceptualEasy

Q26. A B Y 0 0 1 0 1 1 1 0 0 1 1 1 To obtain the given truth table, following logic gate should be placed at G: 2025 (22 Jan Shift 2) JEE Main Previous Year Paper (1) OR Gate (2) AND Gate (3) NOR Gate (4) NAND Gate

2025·MCQEasy

Q28.The output of the circuit is low (zero) for : (A) X = 0, Y = 0 (B) X = 0, Y = 1 (C) X = 1, Y = 0 (D) X = 1, Y = 1 Choose the correct answer from the options given below : (1) (B), (C) and (D) only (2) (A), (B) and (C) only (3) (A), (C) and (D) only (4) (A), (B) and (D) only

2025·MCQEasy

Q45. In the circuit shown here, assuming threshold voltage of diode is negligibly small, then voltage VAB is correctly represented by : (1) VAB would be zero at all times (2) (3) (4)

2025·MCQMedium

NCERT Chapters

  • Class 12 Physics Ch 14: Semiconductor Electronics: Materials, Devices and Simple Circuits